00634nam a22001817a 4500 BD-DhUL 20151029151904.0 151029s2007 BG a|||| m||| 00| 0 eng d BD-DhUL BD-DhUL 004 REA Realization and optimization of reversible arithmetic logic unit / [MS Thesis] Dhaka : University of Dhaka, 2007. vii, 54p. : ill ; 29 cm. Thesis (B.Sc.) - Department of Computer Science and engineering, Universitiy of Dhaka, 2003-04. Includes bibliographical references Computer science ddc REF 42416 42416 0 0 ddc 0 004_000000000000000_REA 1 REF 68909 DUSL DUSL REF 2015-10-29 Gift 004 REA 438629 2015-10-29 1 2015-10-29 REF 0 0 ddc 0 004_000000000000000_REA 1 REF 68910 DUSL DUSL REF 2015-10-29 Gift 004 REA 438630 2015-10-29 2 2015-10-29 REF