<?xml version="1.0" encoding="UTF-8"?>
<metadata
  xmlns="http://example.org/myapp/"
  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
  xsi:schemaLocation="http://example.org/myapp/ http://example.org/myapp/schema.xsd"
  xmlns:dc="http://purl.org/dc/elements/1.1/"
  xmlns:dcterms="http://purl.org/dc/terms/"><dc:Title>Design and test technology for dependable systems-on-chip / Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors.</dc:Title>
<dc:Creator>Ubar, Raimund, 1941-</dc:Creator>
<dc:Creator>Raik, Jaan, 1972-</dc:Creator>
<dc:Creator>Vierhaus, Heinrich Theodor, 1951-</dc:Creator>
<dc:Subject>Systems on a chip Design and construction.</dc:Subject>
<dc:Subject>Networks on a chip. Design and construction.</dc:Subject>
<dc:Subject>Systems on a chip Testing.</dc:Subject>
<dc:Subject>Networks on a chip Testing.</dc:Subject>
<dc:Subject>TK7895.E42 D467 2010</dc:Subject>
<dc:Subject>621.3815 22 UBD</dc:Subject>
<dc:Description>Includes bibliographical references (p. 494-533) and index.</dc:Description>
<dc:Description>"This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"-- Provided by publisher.</dc:Description>
<dc:Publisher>Hershey, PA : Information Science Reference,</dc:Publisher>
<dc:Date>c2010.</dc:Date>
<dc:Date>c2010.</dc:Date>
<dc:Date>2010</dc:Date>
<dc:Type>Text</dc:Type>
<dc:Format>xxv, 550 p. :</dc:Format>
<dc:Language>eng</dc:Language>

</metadata>