05723cam a2200541Ia 4500 ocn915311665 OCoLC 20190328114812.0 m o d cr cnu---unuuu 150801s2015 ne a o 001 0 eng d EBLCP eng pn EBLCP N$T OCLCO OPELS IDEBK YDXCP CDX OCLCF OCLCO DEBSZ OCLCO OCLCQ OCLCO OCLCQ UAB OCLCQ K6U MERUC U3W D6H AU@ COO OCLCQ 9780128008157 (electronic bk.) 0128008156 (electronic bk.) 9780128007273 (OCoLC)915311665 TK7867 TEC 009070 bisacsh 621.3815/48 Seligman, Erik. Formal verification : an essential toolkit for modern VLSI design / [electronic resource] Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar. Amsterdam : Elsevier Science, 2015. 1 online resource (372 pages) : illustrations text txt rdacontent computer c rdamedia online resource cr rdacarrier Includes index. Print version record. Front Cover; Formal Verification; Copyright Page; Contents; Foreword for "Formal Verification: An Essential Toolkit for Modern VLSI Design"; Acknowledgments; 1 Formal verification: from dreams to reality; What Is FV?; Why This Book?; A Motivating Anecdote; FV: The Next Level of Depth; Overall Advantages of FV; General Usage Models for FV; FV for Complete Coverage; FV for Bug Hunting; FV for Exploring Designs; FV in Real Design Flows; FV Methods Not Discussed In This Book; The Emergence of Practical FV; Early Automated Reasoning; Applications to Computer Science. Model Checking Becomes PracticalThe Standardizing of Assertions; Challenges in Implementing FV; Fundamental Limitations of Mathematics; Complexity Theory; The Good News; Amplifying the Power of Formal; Getting the Most Out of This Book; Practical Tips from This Chapter; Further Reading; 2 Basic formal verification algorithms; Formal Verification (FV) in the Validation Process; A Simple Vending Machine Example; Comparing Specifications; Cones of Influence; Formalizing Operation Definitions; Building Truth Tables Intelligently; Adding Sequential Logic; Boolean Algebra Notation. Basic Boolean Algebra LawsComparing Specifications; BDDs; Computing a BDD for a Circuit Design; Model Checking; Boolean Satisfiability; Bounded Model Checking; Solving the SAT Problem; The Davis-Putnam SAT Algorithm; The Davis Logemann Loveland (DLL) SAT Algorithm; Additional SAT Algorithm Improvements; Chapter Summary; Further Reading; 3 Introduction to systemverilog assertions; Basic Assertion Concepts; A Simple Arbiter Example; What are Assertions?; What are Assumptions?; What are Cover Points?; Clarification on Assertion Statements; SVA Assertion Language Basics; Immediate Assertions. Writing Immediate AssertionsComplications of Procedural Code and Motivation for Assert Final; Location in Procedural Blocks; Boolean Building Blocks; Concurrent Assertion Basics and Clocking; Sampling and Assertion Clocking; Sampled Value Functions; Concurrent Assertion Clock Edges; Concurrent Assertion Reset (Disable) Conditions; Setting Default Clock and Reset; Sequences, Properties, and Concurrent Assertions; Sequence Syntax and Examples; Using sequences instead of rose/fell; Property Syntax and Examples; Named Sequences and Properties; Assertions and Implicit Multithreading. Writing the PropertiesPlanning properties at the specification phase; Embedded properties during RTL development; Validation-focused properties; Connecting the properties to your design; Summary; Practical Tips from this Chapter; Further Reading; 4 Formal property verification; What is FPV?; Example for this Chapter: Combination Lock; Bringing Up a Basic FPV Environment; Compiling your RTL; Creating cover points; Creating assumptions; Creating assertions; Clocks and resets; Running the verification; How is FPV Different from Simulation?; What Types and Sizes of Models can be Run? How Do We Reach Targeted Behaviors? Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Electronic circuits Testing. Integrated circuits Very large scale integration Design and construction. Verilog (Computer hardware description language) TECHNOLOGY & ENGINEERING Mechanical. bisacsh Electronic circuits Testing. fast (OCoLC)fst00906898 Integrated circuits Very large scale integration Design and construction. fast (OCoLC)fst00975610 Verilog (Computer hardware description language) fast (OCoLC)fst01165388 Electronic books. Schubert, Tom. Kumar, M. V. Achutha Kiran. Print version: Seligman, Erik. Formal Verification : An Essential Toolkit for Modern VLSI Design. Burlington : Elsevier Science, �2015 9780128007273 ScienceDirect http://www.sciencedirect.com/science/book/9780128007273 247124 247124