Formal verification : an essential toolkit for modern VLSI design - Seligman, Erik.; Schubert, Tom.; Kumar, M. V. Achutha Kiran (Amsterdam : Elsevier Science, 2015)
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity.
Writing the PropertiesPlanning properties at the specification phase; Embedded properties during RTL development; Validation-focused properties; Connecting the properties to your design; Summary; Practical Tips from this Chapter; Further Reading; 4 Formal property verification; What is FPV?; Example for this Chapter: Combination Lock; Bringing Up a Basic FPV Environment; Compiling your RTL; Creating cover points; Creating assumptions; Creating assertions; Clocks and resets; Running the verification; How is FPV Different from Simulation?; What Types and Sizes of Models can be Run?
Includes index.
Print version record.
How Do We Reach Targeted Behaviors?
Keywords: Electronic circuits -- Testing; Integrated circuits -- Very large scale integration -- Design and construction; Verilog (Computer hardware description language); TECHNOLOGY & ENGINEERING -- Mechanical; Electronic circuits -- Testing; Integrated circuits -- Very large scale integration -- Design and construction; Verilog (Computer hardware description language); Electronic books