Formal verification : an essential toolkit for modern VLSI design / [electronic resource] Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar. Seligman, Erik. Schubert, Tom. Kumar, M. V. Achutha Kiran. Electronic circuits Testing. Integrated circuits Very large scale integration Design and construction. Verilog (Computer hardware description language) TK7867 621.3815/48 Includes index. How Do We Reach Targeted Behaviors? Print version record. Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Amsterdam : Elsevier Science, 2015. 2015. 2015 Text 1 online resource (372 pages) : http://www.sciencedirect.com/science/book/9780128007273 eng Formal Verification : An Essential Toolkit for Modern VLSI Design. Formal Verification : An Essential Toolkit for Modern VLSI Design.