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  <titleInfo>
    <title>VHDL for logic synthesis</title>
  </titleInfo>
  <name type="personal">
    <namePart>Rushton, Andrew</namePart>
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  <genre authority="">Electronic books.</genre>
  <genre authority="">Llibres electrònics.</genre>
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    <publisher>Wiley</publisher>
    <dateIssued>2011</dateIssued>
    <edition>3rd ed.</edition>
    <issuance>monographic</issuance>
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    <extent>1 online resource (xvi, 466 pages) : illustrations</extent>
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  <abstract>"Macrocycles: Construction, Chemistry and Nanotechnology Applications is an essential introduction this important class of molecules and describes how to synthesise them, their chemistry, how they can be used as nanotechnology building blocks, and their applications"--</abstract>
  <tableOfContents>Front Matter -- Introduction -- Register-Transfer Level Design -- Combinational Logic -- Basic Types -- Operators -- Synthesis Types -- Std_Logic_Arith -- Sequential VHDL -- Registers -- Hierarchy -- Subprograms -- Special Structures -- Test Benches -- Libraries -- Case Study -- Appendix A: Package Listings -- Appendix B: Syntax Reference -- References -- Index.</tableOfContents>
  <note type="statement of responsibility">Andrew Rushton.</note>
  <note>Includes bibliographical references and index.</note>
  <subject authority="lcsh">
    <topic>VHDL (Computer hardware description language)</topic>
  </subject>
  <subject authority="lcsh">
    <topic>Logic design</topic>
    <topic>Data processing</topic>
  </subject>
  <subject authority="lcsh">
    <topic>Computer-aided design</topic>
  </subject>
  <subject>
    <topic>VHDL (Bilgisayar donanımı tanımlama dili)</topic>
  </subject>
  <subject>
    <topic>Mantık tasarımı</topic>
    <topic>Bilgi işlem</topic>
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  <subject>
    <topic>Bilgisayar destekli tasarım</topic>
  </subject>
  <subject>
    <topic>VHDL (Computer hardware description language)</topic>
  </subject>
  <subject>
    <topic>Logic design</topic>
    <topic>Data processing</topic>
  </subject>
  <subject>
    <topic>Computer-aided design</topic>
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    <topic>COMPUTERS</topic>
    <topic>Computer Engineering</topic>
  </subject>
  <subject authority="bisacsh">
    <topic>COMPUTERS</topic>
    <topic>Logic Design</topic>
  </subject>
  <subject authority="bisacsh">
    <topic>TECHNOLOGY &amp; ENGINEERING</topic>
    <topic>Electronics</topic>
    <topic>Circuits</topic>
    <topic>Logic</topic>
  </subject>
  <subject authority="bisacsh">
    <topic>TECHNOLOGY &amp; ENGINEERING</topic>
    <topic>Electronics</topic>
    <topic>Circuits</topic>
    <topic>VLSI &amp; ULSI</topic>
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  <subject authority="fast">
    <topic>Logic design</topic>
    <topic>Data processing</topic>
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  <subject authority="fast">
    <topic>VHDL (Computer hardware description language)</topic>
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    <topic>VHDL (Computer hardware description language)</topic>
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  <subject authority="local">
    <topic>Logic design / Data processing</topic>
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  <subject authority="local">
    <topic>Computer-aided design</topic>
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  <classification authority="lcc">TK7885.7 .R87 2011</classification>
  <classification authority="ddc" edition="22">621.39/5</classification>
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    <titleInfo>
      <title>VHDL for logic synthesis</title>
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      <edition>3rd ed.</edition>
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  <identifier type="isbn">9781119995852</identifier>
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